Terafab

We are building Terafab, a vertically integrated semiconductor factory at an unprecedented scale. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

As a Memory Process Integration Engineer, you will own the integration of unit processes for DRAM and emerging memory technologies, driving density, retention reliability, and manufacturability from early concept through high-volume production. This is a ground-level role at one of the most ambitious fab programs in the world.

• Own end-to-end process integration for DRAM cell structures from capacitor design through full-flow execution and HVM readiness
• Define integration schemes for advanced DRAM nodes (sub-20nm half-pitch) including deep trench or stacked capacitor architectures
• Develop memory cell integration flows optimizing for capacitance density, leakage control, and refresh characteristics
• Partner with process teams (etch, deposition, implant, CMP) to define process windows for memory-specific modules: STI, wordline formation, storage node contact, capacitor dielectric, and cell plate structures
• Develop and maintain process flow documentation, integration decision logs for memory arrays and peripheral circuits
• Lead root cause analysis and systematic yield improvement across full-flow integration splits, including pattern-dependent fail analysis
• Interface with equipment, metrology, and data teams to establish inline monitoring and SPC at key integration checkpoints for memory-critical parameters: capacitance, retention time, junction leakage
• Collaborate with memory circuit design teams to validate sense amplifier margins, refresh timing, and device frequency targets
• Drive integration development for emerging memory technologies (MRAM, RRAM, or 3D DRAM) as Terafab expands memory roadmap
• Support technology transfer and ramp readiness as Terafab scales memory production

• Degree in Electrical Engineering, Materials Science, Chemical Engineering, or equivalent experience
• 5+ years of engineering experience in a high-volume memory fab (DRAM, 3D NAND, or emerging memory)
• Deep knowledge of at least one advanced DRAM node (sub-25nm) and its capacitor integration tradeoffs
• Hands-on experience with memory-specific integration challenges: high aspect ratio etch, capacitor dielectric reliability, storage node contact resistance, retention optimization
• Proficiency with statistical tools (JMP, R, Python) for DOE design, SPC, and memory bit-yield analysis
• Experience with DRAM capacitor architectures: deep trench, stacked capacitor (cylinder or pillar), or high-k dielectric integration
• Familiarity with 3D memory architectures (3D NAND, 3D DRAM) or emerging memory technologies (MRAM, RRAM, FeRAM)
• Experience standing up a new memory process flow from scratch in a greenfield environment
• Demonstrated ability to drive cross-functional alignment across unit process, equipment, and memory design teams
• Ability to travel internationally (10%)